The present invention relates to methods of manufacturing a semiconductor device, and more particularly to methods of manufacturing a semiconductor device, which include a polishing method that is used to form an insulating film or to form interconnects in the insulating film.
With recent miniaturization of semiconductor devices, the intervals between elements and between interconnects connecting the elements have been increasingly reduced. Such reduced intervals have caused problems such as increased capacitance between interconnects and a reduced signal propagation speed. In order to solve these problems and to achieve higher speed operation and lower power consumption, insulating films having a low relative dielectric constant have been used as interlayer films. However, since the insulating films having a low relative dielectric constant have low hardness, scratches are made by chemical mechanical polishing (CMP) that is performed to form interconnects. This reduces manufacturing yield and reliability due to short-circuits between the interconnects.
As a solution to this problem, a method of reducing scratches has been considered as described in Japanese Patent Publication No. 2002-075933. A polishing pad shown in Japanese Patent Publication No. 2002-075933 will be described below with reference to FIG. 8.
As shown in FIG. 8, Japanese Patent Publication No. 2002-075933 discloses a semiconductor wafer polishing pad that is formed by stacking together a porous elastic resin layer 1, a resin layer (a second layer) 2, and a layer (a third layer) 3. The porous elastic resin layer 1 is an outermost layer and serves as a polishing layer. The second layer 2 adjoins the porous elastic resin layer 1, and has a higher elastic modulus than the porous elastic resin layer 1. The third layer 3 is located on the opposite side of the second layer 2 from the porous elastic resin layer 1, and is sufficiently softer than the second layer 2.